The present invention relates to a semiconductor memory device, particularly to a multi-purpose register (MPR) of the semiconductor memory device which is a circuit that can control bit rate of information output from the MPR and reduce current consumption for outputting the information from the MPR.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies become more advanced, semiconductor memory devices are required to input and output data at higher speed. In order to obtain faster and stable operations, semiconductor memory devices include a variety of circuits for additional operations such as sensing internal temperature, in addition to a core region and a peripheral region for performing data input/output operation.
Consequently, the semiconductor memory devices are required to have the MPR in order to store information for these additional operations.
FIG. 1 is a block diagram for illustrating the MPR 140 in the conventional semiconductor memory device.
Referring to FIG. 1, the MPR 140 may be connected to a data output path 120 including a plurality of data output pads DQ, according to an operation mode.
Specifically, in a normal mode NORMAL_MODE, the core region 100 is connected to the data output path 120 to output data stored in the core region 100 from the semiconductor memory device. In this case, because the MPR 140 is not connected to the data output path 120, information in the MPR 140 are not output from the semiconductor memory device.
In an information output mode MPR_MODE, the MPR 140 is connected to the data output path 120 to output the information in the MPR 140 from the semiconductor memory device. In this case, since the core region 100 is not connected to the data output path 120, the data in the core region 100 are not output from the semiconductor memory device.
That is, in the normal mode NORMAL_MODE, where basic operations such as data input/output operations of the semiconductor memory device are performed, the MPR 140 stores a series of information. However, in the information output mode MPR_MODE, the MPR 140 outputs the information from the semiconductor memory device.
TABLE 1ReadMR3MR3BurstAddressA[2]A[1:0]FunctionLengthA[2:0]Burst Order and Data Pattern100bReadBL = 8000bBurst Order 0, 1, 2, 3, 4, 5, 6, 7PredefinedPredefined pattern [0, 1, 0, 1, 0, 1, 0, 1]100bPattern forBC4000bBurst Order 0, 1, 2, 3SystemPre-defined pattern [0, 1, 0, 1]100bCalibrationBC4100bBurst Order 4, 5, 6, 7Pre-defined pattern [0, 1, 0, 1]101bRFU———110bRFU———111bThermal000bBurst Order 0, 1, 2, 3, 4, 5, 6, 7111bSensor000bBurst Order 0, 1, 2, 3ReadoutBurst bit 0 is thermal sensor LSB111b100bBurst Order 4, 5, 6, 7Burst bit 7 is thermal sensor MSB (signbit)
Table 1 shows the Joint Electron Device Engineering Council (JEDEC) specification for the MPR 140.
As shown in Table 1, the MPR 140 stores predefined information and temperature information. The predefined information (Read Predefined Pattern For System Calibration) is set to a predetermined value as a reference of an operation of the semiconductor. The temperature information (Thermal Sensor Readout) indicates internal temperature of the semiconductor memory device, which is output from an on die thermal sensor (ODTS).
To this end, the MPR 140 includes a plurality of register units 142 and an information selection unit 144. The plurality of register units 142 are configured to store a plurality of information, respectively, each of the information having multiple bits. The information selection unit 144 is configured to output information stored in one of the plurality of register units 142.
As shown in Table 1, which information is to be output from the MPR 140 is determined by a selection information A[0:2] defined in a memory register set (MRS).
Specifically, an uppermost bit A[2] of the selection information A[0:2] defined in the MRS is used to determine whether to enter the information output mode MPR_MODE or not. That is, when the uppermost bit A[2] of the selection information A[0:2] has a logic high level, the semiconductor memory device enters the information output mode MPR_MODE. When the uppermost bit A[2] of the selection information A[0:2] has a logic low level, the semiconductor memory device exits the information output mode MPR_MODE.
The bits A[0:1] of the selection information A[0:2] defined in the MRS are used to select one of the information stored in the MPR 140 in the information output mode MPR_MODE.
That is, when the bits A[0:1] of the selection information A[0:2] are all have a logic high level, the predefined information (Read Predefined Pattern For System Calibration) is selected. On the contrary, when the bits A[0:1] of the selection information A[0:2] are all have a logic low level, the temperature information (Thermal Sensor Readout) is selected.
In a case where one of the bits A[0:1] has a logic high level and the other has a logic low level, i.e., the bits A[0:1] have different logic levels, information RFU is selected, which can be arbitrarily stored by a user.
In the conventional semiconductor memory device, not only the data in the core region 100, but also the information in the MPR 140 should be output from the semiconductor memory device through the data output path 120. The data output path 120 refers to an internal element of the semiconductor memory device for transferring the data which will be output from the semiconductor memory device. The data output path 120 includes global lines GIOU<0:7> and GIOL<0:7> and data output pads UDQ<0:7> and LDQ<0:7> in FIG. 1.
The data path 120 for the data in the core region 100 is the same element as that for the information in the MPR 140. However, the operation of the data path 120 for the data in the core region 100 is different from the operation of the data path 120 for the information in the MPR 140, which will be described in detail below.
Regarding the data path 120 for the data in the core region 100, the data in the core region 100 are output from the semiconductor memory device through all of the data output pads UDQ<0:7> and LDQ<0:7>. This is because the data in the core region 100 are transferred through the global lines GIOU<0:7> and GIOL<0:7> at the same time.
Regarding the data path 120 for the information in the MPR 140, the information in the MPR 140 are output from the semiconductor memory device only through the data output pads UDQ<0> and LDQ<0>. This is because the information in the MPR 140 are transferred only through the global lines GIOU<0> and GIOL<0>, not through the other global lines GIOU<1:7> and GIOL<1:7>.
In other words, all of the elements of the data path 120 are used for transferring the data in the core region 100. However, only a few elements of the data path 120 are used for transferring the information in the MPR 140. More specifically, for transferring the information in the MPR 140, only the zeroth upper global line GIOU<0>, the zeroth lower global line GIOL<0>, the zeroth upper data output pad UDQ<0> and the zeroth lower data output pad LDQ<0> are used. That is, the other elements including the first to seventh upper global lines GIOU<1:7>, the first to seventh lower global lines GIOL<1:7>, the first to seventh upper data output pads UDQ<1:7> and the first to seventh lower data output pads LDQ<1:7> are not used.
FIG. 2 is a block diagram for illustrating a path for transferring the information in the MPR 140 when connection relations of the global lines and the data output pads are varied according to variations of a data output bandwidth in a conventional semiconductor memory device.
Referring to FIG. 2, as the data output bandwidth is varied to ×16, ×8 and ×4, the connection relations of the global lines GIOU<0:7> and GIOL<0:7> and the data output pads UDQ<0:7> and LDQ<0:7> in the conventional semiconductor memory device are varied.
Specifically, when the data output bandwidth of the semiconductor memory device is ×16, the global lines GIOU<0:7> and GIOL<0:7> are one-to-one connected to the data output pads UDQ<0:7> and LDQ<0:7>.
In more detail, the zeroth upper global line GIOU<0> is connected to the zeroth upper data output pad UDQ<0>. The first upper global line GIOU<1> is connected to the first upper data output pad UDQ<1>. The second upper global line GIOU<1> is connected to the second upper data output pad UDQ<2>. The third upper global line GIOU<3> is connected to the third upper data output pad UDQ<3>. The fourth upper global line GIOU<4> is connected to the fourth upper data output pad UDQ<4>. The fifth upper global line GIOU<5> is connected to the fifth upper data output pad UDQ<5>. The sixth upper global line GIOU<6> is connected to the sixth upper data output pad UDQ<6>. The seventh upper global line GIOU<7> is connected to the seventh upper data output pad UDQ<7>. Similarly, the zeroth lower global line GIOL<0> is connected to the zeroth lower data output pad LDQ<0>. The first lower global line GIOL<1> is connected to the first lower data output pad LDQ<1>. The second lower global line GIOL<2> is connected to the second lower data output pad LDQ<2>. The third lower global line GIOL<3> is connected to the third lower data output pad LDQ<3>. The fourth lower global line GIOL<4> is connected to the fourth lower data output pad LDQ<4>. The fifth lower global line GIOL<5> is connected to the fifth lower data output pad LDQ<5>. The sixth lower global line GIOL<6> is connected to the sixth lower data output pad LDQ<6>. The seventh lower global line GIOL<7> is connected to the seventh lower data output pad LDQ<7>.
In this case, in the normal mode NORMAL_MODE, data in the core region 100 are loaded on all of the global lines GIOU<0:7> and GIOL<0:7>, and the global lines GIOU<0:7> and GIOL<0:7> are directly connected to the data output pads UDQ<0:7> and LDQ<0:7>, respectively. Therefore, the data in the core region 100 are output through the respective data output pads UDQ<0:7> and LDQ<0:7>.
To this end, a first pad selector 200, a second pad selector 220 and a third pad selector 240 are all enabled. Here, the first pad selector 200 is configured to control connections of all of the global lines GIOU<0:3>, GIOU<4:7>, GIOL<0:3> and GIOL<4:7> to the top upper data output pads UDQ<0:3> according to the data output bandwidth. The second pad selector 220 is configured to control connections of the bottom upper global lines GIOU<4:7> and the bottom lower global lines GIOL<4:7> to the bottom upper data output pads UDQ<4:7> according to the data output bandwidth. The third pad selector 240 is configured to control the connections of the lower global lines GIOL<0:7> to the lower data output pads LDQ<0:7> according to the data output bandwidth.
The global lines GIOU<0:7> and GIOL<0:7> are directly connected to the data output pads UDQ<0:7> and LDQ<0:7>, respectively, as described above. However, the information in the MPR 140 used in the information output mode MPR_MODE are loaded only on the zeroth upper global line GIOU<0> and the zeroth lower global line GIOL<0>. Therefore, the information in the MPR 140 are output only through the zeroth upper data output pad UDQ<0> and the zeroth lower data output pad LDQ<0>.
When the data output bandwidth of the semiconductor memory device is ×8, the global lines GIOU<0:7> and GIOL<0:7> are connected to the upper data output pads UDQ<0:7> in two-to-one correspondence.
In other words, the zeroth to seventh lower data output pads LDQ<0:7> are not used. Hence, the zeroth upper global line GIOU<0> and the zeroth lower global line GIOL<0> are connected to the zeroth upper data output pad UDQ<0>. The first upper global line GIOU<1> and the first lower global line GIOL<1> are connected to the first upper data output pad UDQ<1>. The second upper global line GIOU<2> and the second lower global line GIOL<2> are connected to the second upper data output pad UDQ<2>. The third upper global line GIOU<3> and the third lower global line GIOL<3> are connected to the third upper data output pad UDQ<3>. The fourth upper global line GIOU<4> and the fourth lower global line GIOL<4> are connected to the fourth upper data output pad UDQ<4>. The fifth upper global line GIOU<5> and the fifth lower global line GIOL<5> are connected to the fifth upper data output pad UDQ<5>. The sixth upper global line GIOU<6> and the sixth lower global line GIOL<6> are connected to the sixth upper data output pad UDQ<6>. Finally, the seventh upper global line GIOU<7> and the seventh lower global line GIOL<7> are connected to the seventh upper data output pad UDQ<7>.
In this case, in the normal mode NORMAL_MODE, the data in the core region 100 are loaded on all of the global lines including the upper global lines GIOU<0:7> and the lower global lines GIOL<0:7>, as described above. The global lines GIOU<0:7> and GIOL<0:7> are divided to the upper global lines GIOU<0:7> and the lower global lines GIOL<0:7>, and not only the upper global lines GIOU<0:7>, but also the lower global lines GIOL<0:7> are connected to the upper data output pads UDQ<0:7>. Therefore, the data in the core region 100 are output through the upper data output pads UDQ<0:7>.
To this end, the first pad selector 200 is enabled, which is configured to control the connections of all of the global lines GIOU<0:3>, GIOU<4:7>, GIOL<0:3> and GIOL<4:7> to the top upper data output pads UDQ<0:3> according to the data output bandwidth. Also, the second pad selector 220 is enabled, which is configured to control the connections of the bottom upper global lines GIOU<4:7> and the bottom lower global lines GIOL<4:7> to the bottom upper data output pads UDQ<4:7> according to the data output bandwidth. However, the third pad selector 240 is disabled, which is configured to control the connections of the lower global lines GIOL<0:7> to the lower data output pads LDQ<0:7> according to the data output bandwidth.
As described above, the global lines GIOU<0:7> and GIOL<0:7> are divided to the upper global lines GIOU<0:7> and the lower global lines GIOL<0:7>, and not only the upper global lines GIOU<0:7>, but also the lower global lines GIOL<0:7> are connected to the upper data output pads UDQ<0:7>. However, the information in the MPR 140, which are used in the information output mode MPR_MODE, are loaded only on the zeroth upper global line GIOU<0> and the zeroth lower global line GIOL<0>. Therefore, the information in the MPR 140 are output only through the zeroth upper data output pad UDQ<0>.
In order to determine whether the data output through the zeroth upper data output pad UDQ<0> is the data loaded on the zeroth upper global line GIOU<0> or the data loaded on the zeroth lower global line GIOL<0>, a not-used bit of the row address (RA) is utilized.
When the data output bandwidth of the semiconductor memory device is ×4, the global lines GIOU<0:7> and GIOL<0:7> are connected to the zeroth to third upper data output pads UDQ<0:3> in four-to-one correspondence.
In other words, the fourth to seventh upper data output pads UDQ<4:7> and the zeroth to seventh lower data output pads LDQ<0:7> are not used. Hence, the zeroth and seventh upper global lines GIOU<0> and GIOU<7> and the zeroth and seventh lower global lines GIOL<0> and GIOL<7> are connected to the zeroth upper data output pad UDQ<0>. The first and sixth upper global lines GIOU<1> and GIOU<6> and the first and sixth lower global lines GIOL<1> and GIOL<6> are connected to the first upper data output pad UDQ<1>. The second and fifth upper global lines GIOU<2> and GIOU<5> and the second and fifth lower global lines GIOL<2> and GIOL<5> are connected to the second upper data output pad UDQ<2>. The third and fourth upper global lines GIOU<3> and GIOU<4> and the third and fourth lower global lines GIOL<3> and GIOL<4> are connected to the third upper data output pad UDQ<3>.
In this case, only the top upper data output pads UDQ<0:3> are used, and the bottom upper data output pads UDQ<4:7>, the top lower data output pads LDQ<0:3> and the bottom lower data output pads LDQ<4:7> are not used. Thus, in the normal mode NORMAL_MODE, the data in the core region 100 are loaded on all of the global lines GIOU<0:7> and GIOL<0:7>. The global lines are divided to the top upper global lines GIOU<0:3>, bottom upper global lines GIOU<4:7>, top lower global lines GIOL<0:3> and bottom lower global lines GIOL<4:7>. Here, not only the top upper global lines GIOU<0:3>, but also the bottom upper global lines GIOU<4:7>, the top lower global lines GIOL<0:3> and the bottom lower global lines GIOL<4:7> are connected to the top upper data output pads UDQ<0:3>. Therefore, the data in the core region 100 are output through the top upper data output pads UDQ<0:3>.
To this end, the first pad selector 200 is enabled, which is configured to control the connections of all of the global lines GIOU<0:3>, GIOU<4:7>, GIOL<0:3> and GIOL<4:7> to the top upper data output pads UDQ<0:3> according to the data output bandwidth. However, the second pad selector 220 is disabled, which is configured to control the connections of the bottom upper global lines GIOU<4:7> and the bottom lower global lines GIOL<4:7> to the bottom upper data output pads UDQ<4:7> according to the data output bandwidth. In addition, the third pad selector 240 is also disabled, which is configured to control the connections of the lower global lines GIOL<0:7> to the lower data output pads LDQ<0:7> according to the data output bandwidth.
As described above, the global lines GIOU<0:7> and GIOL<0:7> are divided to the top upper global lines GIOU<0:3>, the bottom upper global lines GIOU<4:7>, the top lower global lines GIOL<0:3> and the bottom lower global lines GIOL<4:7>. Here, not only the top upper global lines GIOU<0:3>, but also the bottom upper global lines GIOU<4:7>, the top lower global lines GIOL<0:3> and the bottom lower global lines GIOL<4:7> are connected to the top upper data output pads UDQ<0:3>. However, the information in the MPR 140, which are used in the information output mode MPR_MODE, are loaded only on the zeroth upper global line GIOU<0> and the zeroth lower global line GIOL<0>. Therefore, the information in the MPR 140 are output only through the zeroth upper data output pad UDQ<0>.
In order to determine whether the data output through the top upper data output pads UDQ<0:3> are the data loaded on the upper global lines GIOU<0:7> or the data loaded on the lower global lines GIOL<0:7>, a not-used bit of the row address (RA) is utilized. Furthermore, in order to determine whether the data output through the top upper data output pads UDQ<0:3> are the data loaded on the top global lines GIOU<0:3> and GIOL<0:3> or the data loaded on the bottom global lines GIOU<4:7> and GIOL<4:7>, a not-used bit of the column address (CA) is utilized.
The first to third pad selectors 200, 220 and 240 having the above described configurations allow the data loaded in the global lines GIOU<0:7> and GIOL<0:7> to be appropriately output from the semiconductor memory device, even if the connection relations of the global lines GIOU<0:7> and GIOL<0:7> and the data output pads UDQ<0:7> and GIOL<0:7> are varied according to the data output bandwidth.
The design of the first to third pad selectors 200, 220 and 240 is centered on appropriate outputting of the data in the core region 100. Accordingly, when the information in the MPR 140 are output only through the predetermined global lines GIOU<0> and GIOL<0>, data loaded on the other global lines GIOU<1:7> and GIOL<1:7> are output regardless of what the data are, and ignored because they are meaningless data.
However, the outputting of the meaningless data also consumes current. This means that the semiconductor memory device utilizing the first to third pad selectors 200, 220 and 240 having the above described configurations consumes unnecessary current in the information output mode MPR_MODE.
TABLE 2RACAGAXDB<0>GAXDB<1>GAXDB<2>GAXDB<3>X16XXLLHLX8LXHLLLX8HXLLHLX4LLHLLLX4LHLHLLX4HLLLHLX4HHLLLH
Logic level relations among signals for controlling the first pad selector 200, the second pad selector 220 and the third pad selector 240 are shown in Table 2. Here, as described above, the first pad selector 200 controls the connections of all the global lines GIOU<0:3>, GIOU<4:7>, GIOL<0:3> and GIOL<4:7> to the top lower data output pads LDQ<0:3> according to the data output bandwidth. Also, the second pad selector 220 controls the connections of the bottom upper global lines GIOU<4:7> and the bottom lower global lines GIOL<4:7> to the bottom lower data output pads LDQ<4:7> according to the data output bandwidth, and the third pad selector 240 controls the connections of the lower global lines GIOL<0:7> to the upper data output pads LDQ<0:7> according to the data output bandwidth.
As described above, the MPR 140 of the conventional semiconductor memory device can output the information from the semiconductor memory device through the predetermined data output pads UDQ<0> and LDQ<0> in the information output mode.
Here, since the information are also serial binary data, they should be output from the semiconductor memory device in synchronization with an external clock, like the data in the core region 100.
For example, the MPR 140 used in a double data rate (DDR) semiconductor memory device, which outputs data twice in one cycle of an external clock, should output two bits of the information in one cycle of the external clock through the predetermined data output pads UDQ<0> and LDQ<0>.
Similarly, the MPR 140 used in a double data rate 2 (DDR2) semiconductor memory device, which outputs data four times in one cycle of the external clock, should output four bits of the information in one cycle of the external clock through the predetermined data output pads UDQ<0> and LDQ<0>.
In a case where the semiconductor memory device is installed in a system, such as a personal computer, a server and a notebook computer, there won't be any disruptions in outputting the information in the MPR 140 at a speed corresponding to the operating speed of the semiconductor memory device.
However, when testing the performance of the MPR 140 during the manufacturing of the semiconductor memory device, the outputting of the information in the MPR 140 at the speed corresponding to the operating speed of the semiconductor memory device may cause errors in the test equipment.
As the semiconductor memory device is developed and improved rapidly, the operating speed of the semiconductor memory device is also increased rapidly. Thus, the test equipment for the semiconductor memory device hardly meets the rapidly increasing operating speed of the semiconductor memory device. Therefore, the difference in the operating speeds of the semiconductor memory device and the test equipment thereof may cause test errors while testing the semiconductor memory device during the manufacturing process.
This may be far more serious in the test for outputting the information in the MPR 140, where a test direction may be varied due to the meaningful information, than in the test for outputting the data in the core region 100, where meaningless data may be input/output.